/* Generated automatically by the program `genconstants'
   from the machine description file `md'.  */

#ifndef GCC_INSN_CONSTANTS_H
#define GCC_INSN_CONSTANTS_H

#define ILINK2_REG 30
#define R42_REG 42
#define R55_REG 55
#define R37_REG 37
#define R10_REG 10
#define R34_REG 34
#define LP_COUNT 60
#define R40_REG 40
#define R15_REG 15
#define SP_REG 28
#define ARCV2_ACC 58
#define R44_REG 44
#define R57_REG 57
#define R39_REG 39
#define R1_REG 1
#define R12_REG 12
#define R9_REG 9
#define ILINK1_REG 29
#define R54_REG 54
#define R51_REG 51
#define R49_REG 49
#define MUL32x16_REG 56
#define R47_REG 47
#define R33_REG 33
#define R46_REG 46
#define R59_REG 59
#define R4_REG 4
#define R35_REG 35
#define R3_REG 3
#define CC_REG 61
#define R36_REG 36
#define R30_REG 30
#define R41_REG 41
#define R43_REG 43
#define R56_REG 56
#define R25_REG 25
#define RETURN_ADDR_REGNUM 31
#define PCL_REG 63
#define R32_REG 32
#define R0_REG 0
#define MUL64_OUT_REG 58
#define R53_REG 53
#define R48_REG 48
#define R52_REG 52
#define R16_REG 16
#define R38_REG 38
#define R50_REG 50
#define R45_REG 45
#define R58_REG 58
#define R2_REG 2

enum unspec {
  DUMMY_0 = 0,
  DUMMY_1 = 1,
  DUMMY_2 = 2,
  ARC_UNSPEC_PLT = 3,
  ARC_UNSPEC_GOT = 4,
  ARC_UNSPEC_GOTOFF = 5,
  ARC_UNSPEC_GOTOFFPC = 6,
  UNSPEC_TLS_GD = 7,
  UNSPEC_TLS_LD = 8,
  UNSPEC_TLS_IE = 9,
  UNSPEC_TLS_OFF = 10,
  UNSPEC_ARC_NORM = 11,
  UNSPEC_ARC_NORMW = 12,
  UNSPEC_ARC_SWAP = 13,
  UNSPEC_ARC_DIVAW = 14,
  UNSPEC_ARC_DIRECT = 15,
  UNSPEC_ARC_LP = 16,
  UNSPEC_ARC_CASESI = 17,
  UNSPEC_ARC_FFS = 18,
  UNSPEC_ARC_FLS = 19,
  UNSPEC_ARC_MEMBAR = 20,
  UNSPEC_ARC_DMACH = 21,
  UNSPEC_ARC_DMACHU = 22,
  UNSPEC_ARC_DMACWH = 23,
  UNSPEC_ARC_DMACWHU = 24,
  UNSPEC_ARC_QMACH = 25,
  UNSPEC_ARC_QMACHU = 26,
  UNSPEC_ARC_QMPYH = 27,
  UNSPEC_ARC_QMPYHU = 28,
  UNSPEC_ARC_VMAC2H = 29,
  UNSPEC_ARC_VMAC2HU = 30,
  UNSPEC_ARC_VMPY2H = 31,
  UNSPEC_ARC_VMPY2HU = 32,
  VUNSPEC_ARC_RTIE = 33,
  VUNSPEC_ARC_SYNC = 34,
  VUNSPEC_ARC_BRK = 35,
  VUNSPEC_ARC_FLAG = 36,
  VUNSPEC_ARC_SLEEP = 37,
  VUNSPEC_ARC_SWI = 38,
  VUNSPEC_ARC_CORE_READ = 39,
  VUNSPEC_ARC_CORE_WRITE = 40,
  VUNSPEC_ARC_LR = 41,
  VUNSPEC_ARC_SR = 42,
  VUNSPEC_ARC_TRAP_S = 43,
  VUNSPEC_ARC_UNIMP_S = 44,
  VUNSPEC_ARC_KFLAG = 45,
  VUNSPEC_ARC_CLRI = 46,
  VUNSPEC_ARC_SETI = 47,
  VUNSPEC_ARC_NOP = 48,
  VUNSPEC_ARC_STACK_IRQ = 49,
  VUNSPEC_ARC_DEXCL = 50,
  VUNSPEC_ARC_DEXCL_NORES = 51,
  VUNSPEC_ARC_LR_HIGH = 52,
  VUNSPEC_ARC_EX = 53,
  VUNSPEC_ARC_CAS = 54,
  VUNSPEC_ARC_SC = 55,
  VUNSPEC_ARC_LL = 56,
  VUNSPEC_ARC_BLOCKAGE = 57,
  VUNSPEC_ARC_EH_RETURN = 58,
  VUNSPEC_ARC_ARC600_RTIE = 59,
  VUNSPEC_ARC_ARC600_STALL = 60,
  VUNSPEC_ARC_LDDI = 61,
  VUNSPEC_ARC_STDI = 62,
  UNSPEC_ARC_SIMD_VADDAW = 63,
  UNSPEC_ARC_SIMD_VADDW = 64,
  UNSPEC_ARC_SIMD_VAVB = 65,
  UNSPEC_ARC_SIMD_VAVRB = 66,
  UNSPEC_ARC_SIMD_VDIFAW = 67,
  UNSPEC_ARC_SIMD_VDIFW = 68,
  UNSPEC_ARC_SIMD_VMAXAW = 69,
  UNSPEC_ARC_SIMD_VMAXW = 70,
  UNSPEC_ARC_SIMD_VMINAW = 71,
  UNSPEC_ARC_SIMD_VMINW = 72,
  UNSPEC_ARC_SIMD_VMULAW = 73,
  UNSPEC_ARC_SIMD_VMULFAW = 74,
  UNSPEC_ARC_SIMD_VMULFW = 75,
  UNSPEC_ARC_SIMD_VMULW = 76,
  UNSPEC_ARC_SIMD_VSUBAW = 77,
  UNSPEC_ARC_SIMD_VSUBW = 78,
  UNSPEC_ARC_SIMD_VSUMMW = 79,
  UNSPEC_ARC_SIMD_VAND = 80,
  UNSPEC_ARC_SIMD_VANDAW = 81,
  UNSPEC_ARC_SIMD_VBIC = 82,
  UNSPEC_ARC_SIMD_VBICAW = 83,
  UNSPEC_ARC_SIMD_VOR = 84,
  UNSPEC_ARC_SIMD_VXOR = 85,
  UNSPEC_ARC_SIMD_VXORAW = 86,
  UNSPEC_ARC_SIMD_VEQW = 87,
  UNSPEC_ARC_SIMD_VLEW = 88,
  UNSPEC_ARC_SIMD_VLTW = 89,
  UNSPEC_ARC_SIMD_VNEW = 90,
  UNSPEC_ARC_SIMD_VMR1AW = 91,
  UNSPEC_ARC_SIMD_VMR1W = 92,
  UNSPEC_ARC_SIMD_VMR2AW = 93,
  UNSPEC_ARC_SIMD_VMR2W = 94,
  UNSPEC_ARC_SIMD_VMR3AW = 95,
  UNSPEC_ARC_SIMD_VMR3W = 96,
  UNSPEC_ARC_SIMD_VMR4AW = 97,
  UNSPEC_ARC_SIMD_VMR4W = 98,
  UNSPEC_ARC_SIMD_VMR5AW = 99,
  UNSPEC_ARC_SIMD_VMR5W = 100,
  UNSPEC_ARC_SIMD_VMR6AW = 101,
  UNSPEC_ARC_SIMD_VMR6W = 102,
  UNSPEC_ARC_SIMD_VMR7AW = 103,
  UNSPEC_ARC_SIMD_VMR7W = 104,
  UNSPEC_ARC_SIMD_VMRB = 105,
  UNSPEC_ARC_SIMD_VH264F = 106,
  UNSPEC_ARC_SIMD_VH264FT = 107,
  UNSPEC_ARC_SIMD_VH264FW = 108,
  UNSPEC_ARC_SIMD_VVC1F = 109,
  UNSPEC_ARC_SIMD_VVC1FT = 110,
  UNSPEC_ARC_SIMD_VBADDW = 111,
  UNSPEC_ARC_SIMD_VBMAXW = 112,
  UNSPEC_ARC_SIMD_VBMINW = 113,
  UNSPEC_ARC_SIMD_VBMULAW = 114,
  UNSPEC_ARC_SIMD_VBMULFW = 115,
  UNSPEC_ARC_SIMD_VBMULW = 116,
  UNSPEC_ARC_SIMD_VBRSUBW = 117,
  UNSPEC_ARC_SIMD_VBSUBW = 118,
  UNSPEC_ARC_SIMD_VASRW = 119,
  UNSPEC_ARC_SIMD_VSR8 = 120,
  UNSPEC_ARC_SIMD_VSR8AW = 121,
  UNSPEC_ARC_SIMD_VASRRWi = 122,
  UNSPEC_ARC_SIMD_VASRSRWi = 123,
  UNSPEC_ARC_SIMD_VASRWi = 124,
  UNSPEC_ARC_SIMD_VASRPWBi = 125,
  UNSPEC_ARC_SIMD_VASRRPWBi = 126,
  UNSPEC_ARC_SIMD_VSR8AWi = 127,
  UNSPEC_ARC_SIMD_VSR8i = 128,
  UNSPEC_ARC_SIMD_VMVAW = 129,
  UNSPEC_ARC_SIMD_VMVW = 130,
  UNSPEC_ARC_SIMD_VMVZW = 131,
  UNSPEC_ARC_SIMD_VD6TAPF = 132,
  UNSPEC_ARC_SIMD_VMOVAW = 133,
  UNSPEC_ARC_SIMD_VMOVW = 134,
  UNSPEC_ARC_SIMD_VMOVZW = 135,
  UNSPEC_ARC_SIMD_VABSAW = 136,
  UNSPEC_ARC_SIMD_VABSW = 137,
  UNSPEC_ARC_SIMD_VADDSUW = 138,
  UNSPEC_ARC_SIMD_VSIGNW = 139,
  UNSPEC_ARC_SIMD_VEXCH1 = 140,
  UNSPEC_ARC_SIMD_VEXCH2 = 141,
  UNSPEC_ARC_SIMD_VEXCH4 = 142,
  UNSPEC_ARC_SIMD_VUPBAW = 143,
  UNSPEC_ARC_SIMD_VUPBW = 144,
  UNSPEC_ARC_SIMD_VUPSBAW = 145,
  UNSPEC_ARC_SIMD_VUPSBW = 146,
  UNSPEC_ARC_SIMD_VDIRUN = 147,
  UNSPEC_ARC_SIMD_VDORUN = 148,
  UNSPEC_ARC_SIMD_VDIWR = 149,
  UNSPEC_ARC_SIMD_VDOWR = 150,
  UNSPEC_ARC_SIMD_VREC = 151,
  UNSPEC_ARC_SIMD_VRUN = 152,
  UNSPEC_ARC_SIMD_VRECRUN = 153,
  UNSPEC_ARC_SIMD_VENDREC = 154,
  UNSPEC_ARC_SIMD_VCAST = 155,
  UNSPEC_ARC_SIMD_VINTI = 156
};
#define NUM_UNSPEC_VALUES 157
extern const char *const unspec_strings[];

#endif /* GCC_INSN_CONSTANTS_H */
